Integrated circuit manufacturing typically includes various packaging processes. These packaging processes sometimes involve attaching a die to a substrate and in some of these processes, a substrate is coupled to a backside of a die having through-vias. For example, some packages will include one or more silicon backplane dice having a plurality of electrical ground through-silicon vias located on their backside surfaces. The backside surface of the silicon backplane die being generally coupled to a carrier substrate such as a copper leadframe or a bismaleimide-triazine substrate. In some packaging processes, in order to form such backside vias, typically a die with a via hole (or multiple via holes) disposed on the backside, is placed over an underlying substrate. Disposed on top of the underlying substrate typically is some epoxy-based/organic material-based conductive material, e.g., cure-induced die attach adhesive, conductive die attach paste, or conductive die attach adhesive. Attachment of the die to the underlying substrate generally is accomplished by pressing the die onto the conductive material on top of the underlying substrate. The intent for pressing the die on top of the conductive paste is to fill the via hole with the conductive paste, thus electrically coupling the die to the underlying substrate.
Unfortunately, by using the conventional process, any number of problems may result. For example, cure-induced die attach adhesive may shrink, causing cracking within the adhesive in the via and initiating delamination at leadframe interfaces, with cracking being exacerbated by thermal processing. Conductive die attach paste often is too brittle and lacks durability. Conductive die attach adhesive typically has a much higher coefficient of thermal expansion than do carrier substrates, die, and molding compounds, resulting in severe die warpage after die-attach curing. Furthermore, pressing the die onto an attachment material on an underlying substrate may result in an air pocket or air void at the top of the through silicon via resulting in a partially filled via hole. As a result of these problems, the reliability as well as the electrical and thermal performance of the resulting package may be compromised.